The present invention generally relates to electronic design automation (EDA) for routing interconnections of integrated circuits (ICs) manufactured using a self-aligned double patterning (SADP) process. More specifically, the present invention relates to hierarchical management of self-aligned double patterning cut shapes or “trim shapes.”
Conventional integrated circuits are created by patterning a wafer or substrate to form various devices and interconnections. The process for designing an IC begins generally by hierarchically defining functional components of the circuit using a hardware description language. From this high-level functional description, a physical circuit implementation dataset known as a netlist is created. In its simplest form, a netlist consists of a list of the electronic components in a circuit and a list of the nodes they are connected to (i.e., connectivity information).
A layout file is created using the netlist in a process known as placing and routing. The layout file assigns (i.e., places) logic cells to physical locations in the device layout and a software “router” or circuit designer routes their interconnections. In this manner, component devices and interconnections of the integrated circuit are constructed layer by layer. Once the layout file is generated, each layer is successively deposited onto the wafer and patterned using a photolithography process. These processes leverage one or more photomasks to transfer a layout pattern onto a physical layer on the wafer. Each photomask is created from the layout file of each wafer layer.